Semiconductor devices are becoming smaller and more dense with the evolution of new technology. However, increases in circuit density produce a corresponding challenge to improve chip and chip connections in order to remain competitive. Chip manufacturers are therefore constantly challenged to improve the quality of their products by identifying and improving their products. Whereas significant process improvements are being made by reducing process variability, process improvements alone are not sufficient to increase both yield and reliability of these products.
Electronic products typically comprise a plurality of components. The packaging of these components follow a hierarchy where Integrated Circuit (IC) chips comprising of semiconductor micro-devices are connected (1st level assembly) to carriers made of ceramic or organic laminates comprising one or several layers of metal interconnection lines. These carriers may also contain some other discrete devices like capacitors, resistors etc. Thus assembled carriers with IC chips, along with some kind of sealing and cooling methodology, are called modules. These modules, in turn, are connected to cards (2nd level assembly) usually made of organic laminates with printed circuits on either side of the card. These cards are then connected to boards (3rd level assembly). The number of assembly levels depends mostly on complexity of functions required.
There are three primary 1st level, or chip-level, interconnection technologies, viz., Wire Bonding (WB), Tape Automated Bonding (TAB) and Solder Bonding (SB), such as, for example, C4 (Controlled Collapse Chip Connection).
A number of products presently in the market typically eliminate the first level package by bonding the chips directly onto the card or board. This provides smaller, simpler and lower cost package. For low cost products, the most common method of connecting chips directly on chips has been the Wire Bonding (WB) technique. The Tape Automated Bonding (TAB) has now come to wider use for directly attaching chips on cards or boards because TAB by itself is considered to be the 1st level assembly; and secondly, because of its mechanical flexibility, it is suitable for chip mounting on flexible circuit carriers.
However, with the emergence of Very Large Scale and Ultra Large Scale Integrated Circuit chips, the number of Input/Output (I/O) terminals on a chip has grown so large that not only a close spacing of I/O pads is required but also an array pattern of I/O pads is required.
The requirement of an array pattern renders wire bonding and TAB methods inapplicable.
Another limiting factor for use of these methods is difficulty in testing and/or burning-in of these mounted chips. This difficulty limits the card yield thus making the product expensive.
Yet another shortcoming is that rework is economically unfeasible.
These limitations necessitate use of a C4 like technology for joining chips directly on card.
The C4 or Controlled Collapse Chip Connection technology has been successfully employed for 1st level assembly of chips on ceramic carriers. The C4 technology is described in detail by many authors, see for example, Microelectronics Packaging Handbook, edited by, Rao R. Tummala and Eugene J. Rymaszewski, pages 366-391 (1989), the disclosure of which is incorporated herein by reference.
The C4 interconnection is comprised of two main elements, a solder reflowable pad called Ball Limiting Metallurgy (BLM), and a ball of solder. The BLM is comprised of an adhesive layer like Cr or TiW, and a solder reflowable layer like copper or nickel. The BLM materials and their thicknesses are judiciously chosen to provide good and reliable electrical, mechanical and thermal stability to the interconnect structure. The solder material used for C4 is preferably a low percentage (about 2 percent to about 10 percent) tin alloyed with lead. This combination was initially used to prevent melting of the reflowed solder ball or C4 during the next level of interconnection but now it is mostly used:
(i) to reduce reaction between copper of BLM and tin, as high stresses resulting from excessive copper-tin intermetallic imparts a high stress concentration on underlaying passivation, and,
(ii) for better thermal fatigue characteristic offered by lower Sn percentage.
Presently, there are two problems that limit the use of current C4 technology for 2nd or higher level assembly, i.e., for Direct Chip Attach (DCA) on card. First, it limits the 2nd level interconnection to Pin-Through-Hole (PTH) technology and precludes the use of cost effective, space saving Surface Mount technology (SMT), second because a joining temperature higher than the melting point of the SMT solder is required, the relatively high joining temperature (340.degree. C.-380.degree. C.) will char the card organics.
There are two ways to lower the joining temperature for DCA. One approach is to provide an eutectic (or lower melting) solder on a card metallization. A method pertaining to this approach is described in U.S. Pat. No. 4,967,950 to Legg and Schrottke, which is presently assigned to the assignee of the instant patent application. Legg and Schrottke describes a general scheme for attaching circuit chips to flexible substrate (laminate) using C-4s. The substrate is "tinned" with an alloy of eutectic composition in its contact region with the solder balls on the base of the chip.
The method of pre-coating the card, or an organic carrier, by eutectic solder is taught by Fallon et al., U.S. patent application Ser. No. 08/387,686, entitled "Process for Selective Application of Solder to Circuit Packages", filed on Feb. 13, 1995. In this method, eutectic solder is electroplated on copper conductors of printed circuit card precisely where the Chip C4 bumps would make contact.
A second approach for lowering the joining temperature for Direct Chip Attach (DCA), is to provide a low melting solder on chip C4 rather than on the carrier conductor. Carey et al., in U.S. Pat. No. 5,075,965 and Agarwala et al., in U.S. Pat. Nos. 5,251,806 and 5,130,779, which are presently assigned to the assignee of the instant patent application, and, Japanese Patent Publication No. 62-117346 to Eiji et al., describe various schemes to provide low melting solder on chips.
Carey et al., in U.S. Pat. No. 5,075,965, disclose a method, where an inhomogeneous, anisotropic column consists of lead rich bottom and tin rich top of sufficient thickness to form eutectic alloy. The resulting as-deposited and un-reflowed column is then joined onto the card's conductor.
To circumvent the thermodynamically driven tendency for interdiffusion, Agarwala et al., in U.S. Pat. Nos. 5,251,806 and 5,130,779, showed a structure where the low melt component is separated from the high melt component by interposing a barrier metal layer. This structure does show a hierarchy of solder material, however, in this structure the column of high melting solder never gets reflowed. Because, the stacked solder does not get reflowed there is no metallurgical reaction between the solder stack and the adhesive pad of Ball Limiting Metallurgy (BLM) which is known to cause poor mechanical integrity of the C4 joint.
Eiji et al., in Japanese Patent Publication No. 62-117346, describe an anisotropic column structure of low and high melting solders. The basic objective of this Eiji invention is essentially to provide an increased height of a solder joint rather than to provide a low melting solder joining process. In Eiji et al., a high-melting point metallic layer is secured to a chip and a substrate and a low-melting point metallic layer is then formed. The two low-melting point metallic layers are then joined and thereby the chip is joined to the substrate.
IBM Technical Disclosure Bulletin, entitled "Indium-Lead-Indium Chip Joining", W. A. Dawson et al., Vol. 11, No. 11, page 1528 (Apr. 1969), discloses the standard capping of lead with either indium or tin for diffusion bonding. In order to alleviated the problem of chip collapse onto the surface of the substrate an intermediate temperature is employed.
For the purposes of this invention a bump completely composed of low melting eutectic composition is a feature to be avoided as the high tin content reacts with all of the copper of the adhesive layer (Ball Limiting Metallurgy, BLM) giving a thick intermetallic layer. High stresses of reacted BLM have been known to cause solder pads to fall off and to create insulation cracking. The eutectic solder bumps also have poor electromigration and thermal fatigue lifetime. It is also known that low melting eutectic solder suffers from void formation due to thermal migration which causes circuit failure.
Yet another drawback of an inhomogeneous, anisotropic solder column is that this structure is unfavorable for electrical tests of circuitry before joining the chips on carriers since the electrical probes gouge into the low melt cap during testing and destroy the cap. Furthermore, for the chip burn-in it is also not feasible to use any of the known multi-layered solder balls, since the temperature that is generally used is between 120-150.degree. C. for burn-in which will cause inter diffusion of the low and the high melt components even before the joining operation begins.
This invention, however, relates generally to interconnection in electronic circuit packages, and more particularly to a new solder interconnection, and a method for making the same, for joining an IC chip directly on higher level packages.
According to the present invention a method is provided for attaching IC chips by interaction between an elemental metal and an alloy to spontaneously form a lower melting alloy after the Controlled Collapse Chip Connection (C4) operation.
The invention also relates to providing a reliable metallurgical system for joining the IC chips on rigid or flexible organic microelectronic circuit cards at low temperatures in order to be compatible with the low temperature processing requirement of the organic cards; and, also to be compatible with Surface Mount or Solder Ball Connect Technologies generally used for higher level interconnections.